搜索资源列表
DDS_Ad9854_Verilog
- DDS控制模块 AD9854 VERILOG-DDS control module AD9854 VERILOG
dds_compiler_v4_0
- Verilog的DDS实现正弦波输出。这个模块是不可综合的,但是已经综合了,-Verilog DDS
DDS_TLC5620
- DDS函数信号发生器 tlc5620 verilog-dds tlc5620 verilog
VERILOG_code_for_any_wave_dds
- 编写verilog程序来完成dds,控制任意波形的生成-Write verilog program to complete dds, arbitrary waveform generator control
sss
- 使用Verilog语言编写源代码.调用一些基本的IP核,如DCM模块、DDS模块ChipScope模块、乘法器模块等来实现调制.最后通过编程并利用FPGA板子实现AM、DBS、SSB的调制。-Using Verilog language source code. Invoke some basic IP cores, such as DCM module, DDS module ChipScope modules, multiplier module to achieve modulation.
module-counter8
- 用verilog实现8为计数器频率范围20-80kHz,根据DDS原理来一个时钟计数器记一下,n=n+1,根据公式fout=(fc÷x)÷2,fout=80 fc=320,所以n≥2时,再取反,又由公式 fout=(k.fc)÷2^n,k=50hz,fout=80khz,fc=320,所以数据的位宽n≥7。 设计要求两路方波信号的相位差在0-360゜可调,可以根据延时来实现。具体的-8 is realized with verilog counter frequency range 20-8
Codes-and-Reports
- Verilog Source code for arbitrary waveform generator- simple DDS algorithm codes run on Xilinx Spartan-3E fpga to show output on dac pin. Please see the included report. its really simple to implement. all source code is given.
Sawtooth_Wave
- verilog写的锯齿波程序,基于DDS原路的。内含testbench仿真文件。功能十分强大-verilog write sawtooth program, based on the same route of DDS. Embedded testbench simulation files. Is very powerful
six_wave
- 产生六种波形的DDS信号发生器,用verilog实现,有modersim仿真程序和结果,产生正玄波,方波,锯齿波,三角波,阶梯波。实现完全可用-the dds can output six signal,write in verilog。
CfgDDS_9910
- dds ad9910配置的verilog hdl程序,模块化设计,输入待配置的数据,字长,启动信号,即可自动产生时序,完成一次配置,模块还有done握手信号,方便用户调用时,反复多次配置。-dds ad9910 configuration verilog hdl program, modular design, the input data to be configured, word length, the start signal, the timing can be automatical
QAM_verilog
- 基于FPGA的16QAM,用verilog编写,其中DDS为自己编写,含设计文件和testbench。已通过moldesim软件仿真。 -FPGA-based 16QAM, with verilog writing, including DDS for their preparation, including design files and testbench. Simulation software has been through moldesim.
squre_generate
- 该程序使用Verolog HDL 语言编写,是一个使用DDS原理产生方波的程序,该程序还提供三个按键来改变频率。-This program is developed by Verilog HDL, and is used to generate a squre waveform of any frequancy. This program provide three buttons to change the frequency.
eetop.cn_dds
- 基于verilog的DDS设计,内附代码,仿真环境等说明-the DDS design based on verilog
DDS_TEXT1_1.1
- dds用Verilog代码实现,很适合做信号处理的同学借用。-DDS with Verilog code, it is suitable for signal processing of the students to borrow.
DDS_sin
- 这是一个用Verilog编写的以实现DDS功能的程序,包含了正弦、方波、锯齿波。-This is a Verilog written procedures to implement DDS functions, including sine, square wave, sawtooth.
DPSK_modulate
- verilog实现DPSK的调制是基于DDS直接频率生成-verilog realize DPSK modulation
DDDDDDDDDSSS
- FPGA实现DDS正弦波、方波、三角波发生器Verilog程序(已验证)Quartus工程文件-FPGA realization DDS sine, square, triangle wave generator Verilog program (verified) Quartus Project Files
vftvdr
- 基于FPGA的DDS信号发生器设计,包含Quartus 的工程,打开即可使用,Verilog 语言编写!-The DDS signal generator based on FPGA design, including the Quartus project, open to use, Verilog language! 朗读 显示对应的拉丁字符的拼音 字典- 查看字典详细内容-FPGA design, including the Quartus project, open to use, Ve
dac_900
- DAC900芯片驱动的Verilog语言描述,亲测可用。另外的是FIR滤波代码和DDS波形发生器的代码。既可单独使用,也可以整合在一起。-DAC900 chips driven Verilog language descr iption, pro-test available. Another is the FIR filter code and DDS waveform generator code. Either used alone or can be integrated.
Gen_Square
- 利用DDS技术产生100~1MHz的方波 利用DDS技术产生100~1MHz的方波-generate 100Hz ~ 1MHz square with DDS,using verilog HDL generate 100~1MHz square with DDS,using verilog HDL generate 100~1MHz square with DDS,using verilog HDL